Semiconductor integrated circuit device and manufacturing method thereof

ABSTRACT

An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate ( 1 ). The memory-cell selection MISFET (Qs) has an insulated gate electrode ( 7 ) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate ( 1 ) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode ( 7 ) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate ( 1 ) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductorintegrated circuit devices and manufacturing architectures of the same.More particularly but not exclusively, the invention relates to thosetechnologies adaptable for use with semiconductor integrated circuitdevices having dynamic random access memory (“DRAM”) modules.

BACKGROUND OF THE INVENTION

[0002] Currently available DRAMs are typically designed to include anarray of rows and columns of memory cells-as disposed in a matrix formon a principal surface of a semiconductive substrate at those crosspoints or “intersections” between a plurality of word lines and aplurality of bit lines, wherein each of the memory cells consistsessentially of a capacitive element for accumulation of information anda metal insulator semiconductor field effect transistor (MISFET) for usein selecting a single memory cell, which is serially connected to thecapacitive element. The memory cell selecting MISFET is formed in anactive region of the semiconductor substrate which is surrounded at itsperiphery by an element separation or isolation region. The MISFET isgenerally designed to consist of a gate oxide film and a gate electrodeintegral with a corresponding one of the word lines plus a pair ofsemiconductor active regions for use as a source and drain of thetransistor. A bit line is disposed to overlie the memory cell selectingMISFET in a manner such that it is electrically connected to one of thesource and drain which is commonly shared by two memory cell selectionMISFETs. The information accumulation capacitive element is laid out ata location overlying the memory cell select MISFET and is electricallycoupled to the remaining one of the source and drain.

[0003] A DRAM device with the memory cell structure of this type hasbeen disclosed in Published Unexamined Japanese Patent Laid-Open No.5-291532 and other publications. The memory cells of the DRAM asdisclosed therein are designed so that word lines are increased in widthor made “fat” in active regions (the regions in each of which a wordline serves as the gate electrode of a memory cell select MISFET) andreduced in width or “thinned” in the remaining regions in order toretain the required gate length when miniaturizing or “downsizing” thememory cell select MISFETs while at the same time minimizing the pitchof word lines.

[0004] In addition, the DRAM memory cells as taught by the JapaneseApplication above is arranged so that the bit lines are partly fattenedto extend up to those portions overlying the active regions and that aplanar pattern of such active regions is designed into a gull-wing shapewith part of it being bent toward the bit line side in order to achievesuccessful electrical conduction of more than one contact hole for usein connecting between one of the source and drain of a memory cellselect MISFET and its corresponding bit line operatively associatedtherewith.

[0005] Regrettably the DRAM memory cells taught by the above JapaneseApplication is faced with a problem as to an inability to provide anyexcellent size/dimension accuracy when partly increasing the widths ofword lines and bit lines or when employing the gullwing-shaped planarpattern of the active regions due to the fact that presently availablephotolithography techniques suffer from difficulties in accuratelyachieving ultra-fine resolution of curved-line patterns and/orfolded-line patterns in cases where the minimal fabricatable sizebecomes at or near a limit of resolution in photolithography processesas a result of further progressing in microfabrication orminiaturization of such memory cells. Another problem faced with theprior art DRAM device is that as a through-going hole for use inconnecting between the lower-side electrode of an informationaccumulation capacitive element and the remaining one of the source anddrain of its associated memory cell select MISFET is inherently disposedbetween a bit line and a bit line, partly fattening the bit lines makesit difficult to attain the intended through-hole opening margin, whichleads to incapability of assuring elimination of unwanted electricalshort-circuiting between the lower-side electrode within a though-holeand its associative one of the bit lines.

[0006] It is therefore an object of the present invention to provide aspecific technique for enabling achievement of further miniaturizedmemory cells of a DRAM.

[0007] The foregoing and other objects and inventive features of thisinvention will become more apparent in the following description andaccompanying drawings.

DISCLOSURE OF THE INVENTION

[0008] Some representative ones of the inventions as disclosed hereinwill be explained in brief below.

[0009] (1) A semiconductor integrated circuit device incorporating theprinciples of the invention is arranged to a semiconductor integratedcircuit device comprising a plurality of word lines extending in a firstdirection on a principal surface of a semiconductive substrate, aplurality of bit lines extending in a second direction at right anglesto the first direction, and an array of memory cells of a DRAM asdisposed at cross points of said word lines and said bit lines, eachsaid memory cell including a serial combination of a memory cellselecting MISFET with a gate electrode as integrally formed with acorresponding one of said word lines and a capacitive element forinformation accumulation, wherein said plurality of word lines arearranged to linearly extend in the first direction on the principalsurface of said semiconductive substrate with an identical width, andwherein a distance between adjacent ones of said word lines is less thansaid width.

[0010] (2) The semiconductor integrated circuit device of the inventionis such that the distance between the adjacent ones of said gateelectrodes is set at a minimal size as determinable by a resolutionlimit of photolithography.

[0011] (3) The semiconductor integrated circuit device of the inventionis such that said word lines and the gate electrode of said memory cellselecting MISFET as integrally formed with a corresponding one of saidword lines are comprised of a conductive film at least partiallyincluding a metallic film therein.

[0012] (4) The semiconductor integrated circuit device of the inventionis such that said semiconductive substrate has an active region withsaid memory cell selecting MISFET formed therein and being arranged tohave an island-like pattern extending in the second direction on theprincipal surface of said semiconductive substrate while having itsperiphery as surrounded by an element isolation region.

[0013] (5) The semiconductor integrated circuit device of the inventionis such that the element isolation region surrounding said active regionis formed of an element separation groove having a dielectric filmembedded therein as defined in the principal surface of saidsemiconductive substrate.

[0014] (6) The semiconductor integrated circuit device of the inventionis such that said bit lines are formed overlying said memory cellselecting MISFET with an insulative film laid there between, wherein acontact hole for electrical connection between one of a source and drainof said memory cell selecting MISFET and a corresponding one of said bitlines is formed in self-alignment with the gate electrode of said memorycell selecting MISFET.

[0015] (7) The semiconductor integrated circuit device of the inventionis such that said information accumulation capacitive element is formedto overlie said memory cell selecting MISFET with an insulative filmlaid therebetween, wherein a contact hole for electrical connectionbetween the other of the source and drain of said memory cell selectingMISFET and one electrode of said information accumulation capacitiveelement is formed in self-alignment with the gate electrode of saidmemory cell selecting MISFET.

[0016] (8) The present invention also provides a semiconductorintegrated circuit device comprising a plurality of word lines extendingin a first direction on a principal surface of a semiconductivesubstrate, a plurality of bit lines extending in a second direction atright angles to the first direction, and an array of DRAM memory cellsas disposed at intersections of said word lines and said bit lines, eachsaid memory cell including a serial combination of a memory cellselecting MISFET with a gate electrode as integrally formed with acorresponding one of said word lines and a capacitive element forinformation accumulation, wherein said bit lines straightly extend inthe second direction on the principal surface of said semiconductivesubstrate with an identical width and wherein a distance betweenadjacent ones of said bit lines is greater than said width.

[0017] (9) The semiconductor integrated circuit device of the inventionis such that the width of each said bit line is equal to or less than aminimal size determinable by a resolution limit of photolithography.

[0018] (10) The semiconductor integrated circuit device of the inventionis such that said bit lines are comprised of a conductive film at leastpartially containing a metallic film.

[0019] (11) The invention further provides a semiconductor integratedcircuit device comprising a plurality of word lines extending in a firstdirection on a principal surface of a semiconductive substrate, aplurality of bit lines extending in a second direction at right anglesto the first direction, and an array of DRAM memory cells as disposed atintersections of said word lines and said bit lines, each said memorycell including a serial combination of a memory cell selecting MISFETwith a gate electrode as integrally formed with a corresponding one ofsaid word lines and a capacitive element for information accumulation,wherein an active region with said memory cell selecting MISFET formedtherein is arranged to have an island-like pattern extending in thesecond direction on the principal surface of said semiconductivesubstrate while having its periphery as surrounded by an elementisolation region, wherein said plurality of word lines extend along thefirst direction on the principal surface of said semiconductivesubstrate with an identical width at a distance between adjacent onesthereof, wherein certain one of said bit lines as formed overlying saidelement isolation region with a first insulative film laid therebetweenextends in the second direction on the principal surface of saidsemiconductive substrate with an identical width at a regular distance,and wherein a first contact hole for electrical connection between oneof a source and drain of said memory cell selecting MISFET as formed insaid active region and its associative one of said bit lines as formedoverlying said element isolation region has a diameter in the firstdirection greater than in the second direction with part thereofarranged to extend to overlie said element isolation region.

[0020] (12) The semiconductor integrated circuit device of the inventionis such that said first contact hole includes a polycrystalline siliconfilm as formed therein, wherein said polycrystalline silicon film isdoped with a chosen impurity equal in conductivity type to the sourceand drain of said memory cell selecting MISFET.

[0021] (13) The semiconductor integrated circuit device of the inventionis such that the corresponding one of said bit lines and said one of thesource and drain of said memory cell selecting MISFET are electricallyconnected together via a first through-hole as formed in a secondinsulative film sandwiched between said bit lines and said firstinsulative film.

[0022] (14) The semiconductor integrated circuit device of the inventionis such that the width of said bit lines is less than a diameter of saidfirst through-hole.

[0023] (15) The semiconductor integrated circuit device of the inventionis such that said first contact hole has a diameter in the firstdirection greater than in the second direction, where a portion of thecontact hole consists essentially of a first region extending to overliesaid element isolation region and a second region as formed beneath saidfirst region to have a diameter in the first direction and a diameter inthe second direction being substantially equal thereto, wherein saidfirst region is formed overlying said memory cell selecting MISFET.

[0024] (16) The semiconductor integrated circuit device of the inventionis such that said information accumulation capacitive element is formedover said bit lines with a third insulative film laid therebetween andis electrically connected to a remaining one of the source and drain ofsaid memory cell selecting MISFET via a second through-hole formed insaid third insulative film and a second contact hole as formed in saidfirst insulative film at a location underlying said second through-hole.

[0025] (17) The semiconductor integrated circuit device of the inventionis such that said second contact hole includes a polycrystalline siliconfilm being embedded therein and doped with an impurity equal inconductivity type to the source and drain of said memory cell selectingMISFET.

[0026] (18) The semiconductor integrated circuit device of the inventionis such that said second through-hole is disposed between neighboringones of said bit lines and is formed in self-alignment therewith.

[0027] (19) A semiconductor integrated circuit device of the presentinvention comprises: an array of memory cells each including a serialcombination of a MISFET for memory cell selection having a source anddrain plus insulated gate electrode and a capacitive element for datastorage having first and second electrodes with a dielectric film laidtherebetween; word lines including first, second and third onesextending in a first direction on a principal surface of asemiconductive substrate and each having part used as the gate electrodeof its associated memory cell selecting MISFET; and, bit lines includingfirst and second ones as disposed adjacent to each other to extend in asecond direction at right angles to the first direction on the principalsurface of the semiconductive substrate, wherein the first to third wordlines are substantially identical in width to one another, a distancebetween the first word line and the second word line neighboring theretois substantially equal to a distance between the second word line andthe third word line next thereto, the distance is less than the width,the first and second bit lines are substantially the same as each otherin width, which is greater than the width of these bit lines.

[0028] (20) The semiconductor integrated circuit device of thisinvention further comprises a first conductive layer provided betweenthe first and second word lines for connecting the first bit line toeither one of the source and drain of the memory-cell selecting MISFETand a second conductive layer laid between the second and third wordlines for connecting the remaining one of the source and drain of thememory-cell selecting MISFET to the first electrode of the data storagecapacitive element, wherein the aforesaid one of the source and drain ofthe memory-cell selecting MISFET and the first conductive layer are inself-alignment with the first word line and the second word line whereasthe remaining one of the source and drain of the memory-cell selectingMISFET and the second conductive layer are self-aligned with the secondword line and the third word line.

[0029] (21) The invention further provides a method for manufacturing asemiconductor integrated circuit device comprising a plurality of wordlines extending in a first direction on a principal surface of asemiconductive substrate, a plurality of bit lines extending in a seconddirection at right angles to the first direction, and an array of DRAMmemory cells as disposed at intersections of said word lines and saidbit lines, each said memory cell including a serial combination of amemory cell selecting MISFET with a gate electrode as integrally formedwith a corresponding one of said word lines and a capacitive element forinformation accumulation, said method comprising the steps of:

[0030] (a) forming on the principal surface of said semiconductivesubstrate of a first conductivity type an element isolation region andan active region of island-like pattern having its periphery surroundedby said element isolation region and extending along the seconddirection on the principal surface of said semiconductive substrate;

[0031] (b) patterning a first conductive film formed over the principalsurface of said semiconductive substrate to form word lines extending inthe first direction on the principal surface of said semiconductivesubstrate to have a distance between adjacent ones thereof being lessthan a width of each said word line; and

[0032] (c) forming a source and a drain of said memory cell selectingMISFET by introducing an impurity of a second conductivity type into theprincipal surface of said semiconductive substrate.

[0033] (22) In the semiconductor integrated circuit device manufacturingmethod of the present invention, the gate electrodes are fabricated sothat the distance of adjacent ones thereof is set at a minimal sizedeterminable by a resolution limit in photolithography.

[0034] (23) The semiconductor integrated circuit device manufacturingmethod is arranged to include, after said step (c), further processsteps of:

[0035] (d) forming a first insulative film overlying said memory cellselecting MISFET and then forming a second insulative film overlyingsaid first insulative film and being different in etching rate from saidfirst insulative film;

[0036] (e) etching those portions of said second insulative filmoverlying the source and drain of said memory cell selecting MISFETunder a condition that the etching rate of said second insulative filmwith respect to said first insulative film becomes greater and thenetching said first insulative film overlying the source and drain ofsaid memory cell selecting MISFET to thereby form a first contact holeoverlying one of said source and drain in self-alignment with said gateelectrode to have a diameter in the first direction greater than adiameter in the second direction with part of said first contact holeextending toward said element isolation region while forming a secondcontact hole overlying a remaining one of the source and drain inself-alignment with said gate electrode and having a diameter in thefirst direction substantially the same as its diameter in the seconddirection;

[0037] (f) after having embedded a conductive film in said first contacthole and said second contact hole, forming a third insulative filmoverlying said second insulative film and then forming a firstthrough-hole in said third insulative film at a portion overlying aspecified region extending to said element isolation region of saidfirst contact hole; and

[0038] (g) patterning a second conductive film as formed overlying saidthird insulative film to thereby form bit lines extending along thesecond direction on the principal surface of said semiconductivesubstrate with an identical width at a distance between adjacent ones ofsaid bit lines being greater than said width, and then electricallyconnecting together said first contact hole and a corresponding one ofsaid bit lines via said first through-hole as formed in said thirdinsulative film.

[0039] (24) The semiconductor integrated circuit device manufacturingmethod is such that the width of said bit lines is formed to be equal indimension to or less than a minimal size determinable by aphotolithography resolution limit.

[0040] (25) The semiconductor integrated circuit device manufacturingmethod is arranged to include, after said step (g), further steps of:

[0041] (h) forming a fourth insulative film overlying said bit lines andthen forming a fifth insulative film overlying said fourth insulativefilm at an etching rate different from that of said fourth insulativefilm;

[0042] (i) after having etched said fifth insulative film at a portionoverlying said second contact hole under a condition that the etchingrate of said fifth insulative film relative to said fourth insulativefilm is greater, etching said fourth insulative film at a portionoverlying said second contact hole to thereby form a second through-holeoverlying said second contact hole in self-alignment with acorresponding one of said bit lines; and

[0043] (j) patterning a third conductive film as formed overlying saidfifth insulative film to form a lower-side electrode of an informationaccumulation capacitive element as electrically connected to said secondcontact hole via said second through-hole.

BRIEF DESCRIPTION OF THE DRAWINGS

[0044]FIG. 1 is a diagram depicting equivalent circuitry of a DRAMdevice in accordance with Embodiment 1 of the present invention.

[0045]FIG. 2 is a diagram schematically showing a plan view of majorpart of a memory array of the DRAM in accordance with the Embodiment 1of this invention.

[0046]FIG. 3 is a diagram showing an enlarged plan view of a portion ofthe FIG. 2.

[0047]FIG. 4 is a diagram showing a sectional view of a semiconductorsubstrate along both line A-A′ line and B-B′ of FIG. 3.

[0048] FIGS. 5 to 7 are each a diagram illustrating, in cross-section,main part of the semiconductor substrate at a process step in themanufacture of memory cells of the DRAM of the Embodiment 1 of theinvention.

[0049]FIG. 8 is a diagram depicting a plan view of the main part of thesemiconductor substrate at the step during manufacture of the DRAMmemory cells of Embodiment 1 of the invention.

[0050]FIGS. 9 and 10 are each a diagram depicting in cross-section mainpart of the semiconductor substrate at a step during manufacture of theDRAM memory cells of Embodiment 1 of the invention.

[0051]FIG. 11 is a diagram showing in plan view main part of thesemiconductor substrate at the step during manufacture of the DRAMmemory cells of Embodiment 1 of the invention.

[0052] FIGS. 12 to 14 are each a diagram showing in cross-section mainpart of the semiconductor substrate at a process step during manufactureof the DRAM memory cells of Embodiment 1 of the invention.

[0053]FIG. 15 is a diagram showing, in plan view, main part of thesemiconductor substrate at the step during manufacture of the DRAMmemory cells of Embodiment 1 of the invention.

[0054]FIGS. 16 and 17 are each a diagram showing in cross-section mainpart of the semiconductor substrate at a step during manufacture of theDRAM memory cells of Embodiment 1 of the invention.

[0055]FIG. 18 is a diagram depicting, in plan view, main part of thesemiconductor substrate at the step during manufacture of the DRAMmemory cells of Embodiment 1 of the invention.

[0056]FIG. 19 is a diagram showing in cross-section main part of thesemiconductor substrate at a step during manufacture of the DRAM memorycells of Embodiment 1 of the invention.

[0057]FIG. 20 is a diagram showing in plan view main part of thesemiconductor substrate at the step during manufacture of the DRAMmemory cell of Embodiment 1 of the invention.

[0058] FIGS. 21 to 24 are each a diagram showing in cross-section mainpart of the semiconductor substrate at a step during manufacture of theDRAM memory cell of Embodiment 1 of the invention.

[0059]FIG. 25 is a diagram showing a plan view of the main part of thesemiconductor substrate at the step during manufacture of the DRAMmemory cell of Embodiment 1 of the invention.

[0060] FIGS. 26 to 30 are each a diagram showing in cross-section mainpart of the semiconductor substrate at a step during manufacture of theDRAM memory cell of Embodiment 1 of the invention.

[0061]FIG. 31 is a diagram showing a plan view of the main part of asemiconductor substrate at a step in the manufacture of a memory cell ofa DRAM of Embodiment 2 of the invention.

[0062]FIG. 32 is a diagram showing in cross-section main part of thesemiconductor substrate at a step during manufacture of the DRAM memorycell of Embodiment 2 of the invention.

[0063]FIG. 33 is a diagram depicting an enlarged plan view of the mainpart of the semiconductor substrate at a step during manufacture of theDRAM memory cell of Embodiment 2 of the invention.

[0064] FIGS. 34 to 36 are each a diagram showing in cross-section mainpart of the semiconductor substrate at a step during manufacture of theDRAM memory cell of Embodiment 2 of the invention.

[0065]FIG. 37 is a diagram showing plan view of the main part of thesemiconductor substrate at a process step during manufacture of the DRAMmemory cell of Embodiment 3 of the invention.

[0066] FIGS. 38 to 42 are each a diagram showing in cross-section mainpart of the semiconductor substrate at a process step during manufactureof the DRAM memory cell of Embodiment 3 of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0067] Several preferred embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings below.Note that in the following description, like reference characters areused to designate like parts or components with similar functionalitiesand any repetitive explanation will be eliminated for purposes ofbrevity.

[0068] (Embodiment 1 )

[0069]FIG. 1 is a diagram illustrating electrical equivalent circuitryof a dynamic random access memory (DRAM) device in accordance with oneembodiment of the present invention. As shown herein, the DRAM chipincludes a memory array (MARY) that is configured from a plurality ofmemory cells (MC) organized into a matrix form at those intersectionsbetween a plurality of word lines WL (WLn−1, WLn, WLn+1 . . . ) and aplurality of bit lines BL. A single memory cell for storing therein a1-bit information or data is comprised of a serial combination of acapacitive element C for information accumulation and a metal insulatorsemiconductor field effect transistor (MISFET) Qs for memory cellselection. The memory-cell selecting MISFET Qs has its source and drain,one of which is electrically connected to the information accumulationcapacitive element C and the other of which is electrically coupled to acorresponding one of the bit lines BL. The word lines WL are connectedat certain ends thereof to a word driver circuit WD whereas the bitlines BL are coupled at their selected ends to sense amplifier circuitsSA operatively associated therewith.

[0070]FIG. 2 is a diagram schematically depicting an enlarged plan viewof part of the memory array integrated on the semiconductor substrate;FIG. 3 is an enlarged plan view of part of FIG. 2; and FIG. 4 shows atits left-hand portion a cross-sectional view as taken along line A-A′ ofFIG. 3 and also shows at its right-hand portion a sectional view alongline B-B′ of the same. Note that FIG. 2 and FIG. 3 indicate only thoseconductive layers (expect plate electrodes) which make up the memorycells while illustration of any dielectric films between conductivelayers and on-chip leads overlying the memory cells is eliminatedtherein.

[0071] The memory cells of the DRAM are each formed in a p-type well 2that is formed on the principal surface of a semiconductive substrate 1of p-type conductivity. The planar size of each memory cell is, forexample, 0.46 μm×0.46 μm. Although not limitatively, the p-type well 2with the memory cell formed therein (memory array) is electricallyseparated from the p-type semiconductor substrate 1 by an n-typesemiconductor region 3 that is formed beneath the well in order toeliminate the influence of noises from circuitry formed in the otherregions of the semiconductor substrate 1 (such as for example aninput/output circuit as part of peripheral circuitry).

[0072] The memory-cell select MISFET Qs of a memory cell may be ann-channel type one which is formed in an active region L of the p-typewell 2. As shown in FIGS. 2 and 3, this active region L is designed tohave an elongate island-like shape that linearly extends along thelateral direction (X direction) in the drawings, wherein its size in theX direction is 1.16 μm whereas the size in up-down direction (Ydirection) is 0.24 μm. In case the active region L is designed into suchsimple straight line pattern, any hard-to-resolve ultrafine pattern willno longer take place even when downsizing or miniaturization is done tothe extent that is equivalent to a limit of resolvability inphotolithography techniques, which makes it possible to achieve gooddimension accuracy required. It is noted here that the dimensions of theactive region L and of respective constituent components of a memorycell as will be discussed later are mere examples and should not be usedfor purposes of limitative interpretation of the present invention.

[0073] As shown in FIG. 4, an element isolation region surrounding theactive region L consists essentially of an element separation groove 5,which may be a shallow groove defined in the p-type well 2 with asilicon oxide film 4 embedded therein. The silicon oxide film 4 buriedin the element separation groove 5 is planarized so that its top surfaceis substantially identical in height to the surface of the active regionL—namely the film 4 is flush with active region L. As the elementisolation region comprised of such element separation groove 5 has nosharp edges known as “bird's beaks” in the semiconductor art atterminate end portions of the active region, the effective area of theactive region L may be increased as compared to the same-size elementisolation region (field oxide film) as formed by the conventional localoxidation of silicon (LOCOS) process (selective oxidation method).

[0074] In each active region L, two neighboring memory-cell selectMISFETs Qs are formed and aligned in the X direction with either one ofthe source and drain commonly shaped thereby. One memory-cell selectMISFET Qs consists mainly of a gate oxide film 6 and an insulated gateelectrode 7 as well as a pair of n-type semiconductor regions 8, 8forming the source and drain thereof.

[0075] As shown in FIGS. 2-3, the gate electrode 7 of the memory-cellselect MISFET Qs is formed integrally with a corresponding one of theword lines WL to extend straightly (linearly) in the Y direction up tothe terminate end of the memory array with the same width and samedistance or interval retained along the length thereof. The width of thegate electrode 7 (word line WL), or gate length, is arranged to have asize (0.24 μm, for example) capable of suppressing the so-calledshort-channel effect of the memory-cell select MISFET Qs to therebyallow the threshold voltage to be more than or equal to a prespecifiedvalue. In addition, the distance or interval of two neighboring gateelectrodes 7 (word lines WL) is set designed to be a minimal sizedeterminable by the photolithography resolution limit (0.22 μm, forexample), which is shorter than the gate length of the gate electrode 7(word line WL). In case the gate electrode 7 (word line WL) is designedinto such simple straight line pattern, it is possible to achieveexcellent size accuracy even when the distance thereof is highlyminiaturized or shrunk down at the photolithography resolution limitlevel.

[0076] The gate electrode 7 (word line WL) is constituted for examplefrom a multilayer structure (polymetal structure) of a low-resistivitypolycrystalline silicon film with a chosen n-type impurity such as forexample phosphorus (P) doped thereinto and a tungsten (W) filminsulatively stacked thereover with a TiN film sandwiched between them.In case the gate electrode 5 (word line WL) is partly comprised of suchlow-resistivity metal (W), the resultant sheet resistivity may bereduced to approximately 2 ω/□, which in turn enables suppression of anypossible word line delay. Additionally, as such word line delay may besuppressed without backplating the gate electrode 5 (word line WL) byuse of any low-resistivity metal lead, it becomes possible to reduce byone the requisite number of those lead layers as formed overlying thememory cells involved.

[0077] The gate electrodes 7 (word lines WL) are covered at their upperportions by a silicon nitride film 9, wherein another silicon nitridefilm 10 is formed on the side walls of this silicon nitride film 9 andof gate electrode 7 (word line WL) and also on the surface of theelement separation groove 5. A double-layered structure of silicon oxidefilms 11, 12 is formed to overlie the silicon nitride film 9 that coversthe gate electrode 7 (word line WL), the upper film 12 of which isplanarized in such a manner that its surface is substantially identicalin height with respect to an overall surface area of the semiconductorsubstrate 1.

[0078] At a location overlying a pair of n-type semiconductor regions 8making up the source and drain of a memory-cell select MISFET Qs,contact holes 13 and 14 are formed which extend through the siliconoxide films 12, 11 and gate oxide film 6 to reach the n-typesemiconductor regions 8. These contact holes 13, 14 are filled withplugs (conductive layers) 15 embedded therein, which are made oflow-resistivity polysilicon film components with a chosen impurity ofn-type conductivity (phosphorus (P), for example) doped therein.

[0079] The contact holes 13, 14 and the plugs (conductive layers) 15 areformed so that each is self-aligned with the silicon nitride film 10against the gate electrode 7 (word line WL). More specifically, thediameter of each contact hole 13, 14 at the bottom portion thereof inthe X direction is equal in dimension to a distance between the siliconnitride film 10 on the sidewall of one of two neighboring gateelectrodes 7 (word lines WL) and the silicon nitride film 10 on thesidewall of a remaining one thereof. It is required that the siliconnitride film 10's thickness in the X direction be at least a specificfilm thickness capable of preventing leakage between the plugs(conductive layers) 15 within the contact holes 13, 14 and gateelectrodes 7 (word lines WL), which thickness typically measures 0.05μm. Accordingly, where the interval or pitch of the gate electrodes 7(word lines WL) is set at a size determinable depending upon thephotolithography resolution limit (here, 0.22 μm), the X-directionaldiameter at the bottom of each contact hole 13, 14 is given as 0.12(=0.22−(0.05×2)) μm, which is less than the resolution limit even at itsmaximal value. Additionally the along-the-x-direction diameter at theupper part of each contact hole 13, 14 is set at 0.24 μm, or more orless. In this way, where the contact holes 13, 14 are each formed inself-alignment with the gate electrode 7 (word lines WL), it becomespossible to ensure successful prevention of any electricalshortcircuiting between such contact holes 13, 14 and gate electrodes 7(word lines WL) even when the distance of gate electrodes 7 (word linesWL) is reduced through advanced microfabrication processes down at thephotolithography resolution limit level. In another word, since thecontact holes 13, 14 and the plugs 15 (conductive layers) are eachformed in self-alignment with the gate electrode 7 (word lines WL), thedistance between the word lines can be set to be a minimal size asdetermined by the resolution limit of the photolithography.

[0080] The contact hole 14, which is one of the above-noted contactholes 13, 14, has its diameter in the Y direction that is the same asthe size (0.24 μm) of the active region L in the Y direction. Incontrast, the along-the-Y-direction diameter of the remaining contacthole (a contact hole overlying the n-type semiconductor region 8 ascommonly shared by two memory-cell select MISFETs Qs) 13 is set at apreselected value (0.48 μm, for example) that is greater than thediameter of the active region L in the Y direction (0.24 μm). In otherwords the contact hole 13 is designed to have a substantiallyrectangular planar pattern wherein the diameter in the Y direction isgreater than the diameter in the X direction (at the upper end portionthereof), part of which is arranged to go out of the active region L andextend up to the upper portion of the element separation groove 5.

[0081] A silicon oxide film 16 is formed overlying the silicon oxidefilm 12 with the contact holes 13, 14 formed therein; further, the bitlines BL are formed overlying it. As shown in FIGS. 2-3 the bit lines BLare disposed overlying the element separation grooves 5 in a manner suchthat they extend straightly (linearly) in the X direction up to theterminate end of the memory array with the same width and same intervalskept along the entire lengths thereof. The pitch of two neighboring bitlines BL is the same as the memory cell size (0.46 μm) in the Xdirection.

[0082] The bit lines BL are such that the distance or intervaltherebetween is longer than the width thereof in order to maximallyreduce any inherent parasitic or stray capacitance that will possibly beformed between adjacent ones of the bit lines BL to thereby improveinformation reading/writing speeds. In other words, letting the bitlines BL decrease in width for widening the distance between neighboringbit lines BL makes it possible to reduce any possible parasiticcapacitance. The distance of bit lines BL is typically set at 0.32 μm.In this case the width of each bit line BL is at 0.14 μm (=0.46−0.32),which is less than the minimum size determinable by the photolithographyresolution limit value. Where the bit lines BL are designed into suchsimple linear pattern, it is possible to attain good size accuracy evenwhen the width thereof is reduced by microfabrication down at thephotolithography resolution limit level. In addition, letting thedistance of bit lines BL be greater than the width thereof makes itpossible, even when the memory cell size is shrunk, to reserve therequired opening margin of through-going holes (those through-holes eachconnecting between an information accumulation capacitive element C andits associated contact hole 14) 21 each disposed at an intersectionbetween a bit line BL and its associative gate electrode 7 as will bedescribed later.

[0083] The bit lines BL are each constituted from a multilayer structureof a TiN film and an overlying W film laminated over each other. In casepart of bit line BL is made of a certain low-resistivity metal (W), itsresultant sheet resistivity may be reduced down at about 2Ω/□ therebyenabling information reading and writing to be performed at high speeds.In addition, as those on-chip leads of peripheral circuitry of the DRAMare manufacturable simultaneously at a process step of fabricating thebit lines BL, it is possible to simplify the manufacturing processes ofsuch DRAM. Further, in case the bit lines BL are comprised of specificmaterials (W, TiN) of greater electro-migration durability, it ispossible to reduce the rate of open-circuit defects even whenminiaturizing the width of the bit lines BL down to a minimal level ator near the photolithography resolution limit level.

[0084] The bit lines BL are arranged so that each is electricallyconnected to the plug (conductive layer 15 within said contact hole 13via a through-hole 17 as formed in the silicon oxide film 16 and isfurther electrically coupled through this plug (conductive layer) 15 tothe n-type semiconductor region 8 (one of the source and drain) ascommonly shared by two memory-cell select MISFETs Qs. The through-hole17 for use in connecting between such bit line BL and its associatedplug (conductive layer) 15 within the contact hole 13 is formedimmediately beneath the bit line BL as disposed overlying the elementseparation groove 5 and is designed to have a diameter that is greaterthan the width of bit line BL. In this way, letting the Y-directionaldiameter of the contact hole 13 be greater than its X-directionaldiameter while at the same time causing part of it to extend up to alocation overlying the element separation groove 5 may ensure successfulelectrical connection between the bit line BL and the n-typesemiconductor region 8 without having to designe either to partiallyfatten the width of bit line BL and let it extend up to the locationoverlying the active region L or to fold part of the active region L inthe direction of bit line BL.

[0085] Silicon oxide films 18, 19 are provided to overlie the bit linesBL; further, a silicon nitride film 20 is formed overlying such films.The silicon oxide film 19 is planarized to ensure that its surface iskept substantially identical in height over the entire area of thesemiconductor substrate 1. Formed over the silicon nitride film 20 isthe information accumulation capacitive element C. The informationaccumulation capacitive element C is formed of a lamination, called astacked structure in the art to which the invention pertains, of alower-side electrode (accumulation electrode) 22 and an intermediatecapacitor dielectric film 23 plus an upper-side electrode (plateelectrode) 24 in this order of sequence as looking at from the lowestlayer. The lower electrode 22 and upper electrode 24 are each made of alow-resistivity polysilicon film with a chosen impurity—phosphorus (P)for example—doped thereinto whereas the capacitor dielectric film 23 isof an insulative film with high resistivity such as tantalum oxide(Ta₂O₅) by way of example.

[0086] As shown in FIGS. 2-3, the lower electrode 22 of the informationaccumulation capacitive element C is designed to have an elongatepattern that linearly extends in the X direction shown in the drawings,wherein it measures 0.77 μm in size in the X direction and 0.31 μm in Ydirection. Additionally a distance between neighboring lower electrodes22 is 0.15 μm in both the X direction and Y direction. In case the lowerelectrode 22 is arranged to have such simple straight line pattern, anyresolution-difficult ultrafine patterns will no longer take place evenwhen the distance is reduced down to the photolithography resolutionlimit level, which in turn makes it possible to attain good sizeaccuracy required.

[0087] The lower electrode 22 of the information accumulation capacitiveelement C is electrically connected to the plug (conductive layer) 15residing within said contact hole 14 via a through-hole 21 as formed topenetrate the silicon nitride film 20 and silicon oxide films 19, 18plus the underlying silicon oxide film 16 and is further electricallycoupled via this plug (conductive layer) 15 to the remaining one of thesource and drain of the memory-cell select MISFET Qs. As thethrough-hole 21 for use in connecting together the lower electrode 22and the plug (conductive layer) 15 within the contact hole 14 is laidout between a bit line BL and another bit line BL next thereto, theopening area of such through-hole 21 is determinable by the distance ofbit lines BL. Where the bit lines BL are designed so that each linearlyextends in the X direction with the same width and same intervalretained along the overall length thereof in the way stated supra, itbecomes possible to ensure elimination or preclusion of any unwantedelectrical shorting between the lower electrode 22 within thethrough-hole 21 and its associated bit line(s) BL due to the fact thatthe required opening margin of such through-hole 21 is obtainable evenwhen the memory cell size is shrunk.

[0088] Although not specifically depicted in the drawings, an interlayerdielectric film is formed overlying the information accumulationcapacitive element C while letting one or a couple of metal leads beformed to overlie such interlayer dielectric film.

[0089] An explanation will next be given of one exemplary manufacturingmethod of the memory cells arranged as discussed above with reference toFIG. 5 through FIG. 30 in the order of process steps. Note that ionimplantation conditions and those values as to thermal processingtemperatures in the following explanation are mere examples and thusshould not be used for purposes of limitative interpretation of theinvention as disclosed and claimed herein.

[0090] Firstly, as shown in FIG. 5, a semiconductive substrate 1 of pconductivity type is prepared which is subjected to thermal processingto form a silicon oxide film 30 on the surface thereof; thereafter, asilicon nitride film 31 is deposited by chemical vapor deposition (CVD)techniques on the silicon oxide film 30. Then, form on the siliconnitride film 31 a photoresist film 32 covering an active region andhaving more than one opening defined therein as an element isolationregion, which photoresist film 32 is used as a mask to pattern thesilicon nitride film 31.

[0091] Next, after having removed away the photoresist film 32, etch thesilicon oxide film 30 and semiconductor substrate 1 with the siliconnitride film 31 being as a mask therefor, thereby forming a groove 5 ain the semiconductor substrate 1 to a depth of approximately 300 to 400nanometers (nm) as shown in FIG. 6.

[0092] Next, as shown in FIGS. 7 and 8, a silicon oxide film 4 isdeposited by CVD techniques on the semiconductor substrate 1 and is thensubject to thermal processing for densification (sintering) at atemperature of about 1,000° C.; thereafter, use knownchemical-mechanical polishing (CMP) techniques to abrade or polish thissilicon oxide film 4 while allowing the groove 5 a to reside inside ofit, thereby forming an element separation groove 5 and active region L.

[0093] After having effectuated wet etching using hot phosphoric acidfor removal of any residual components of the silicon nitride film 31 onthe semiconductor substrate 1 in the active region L, form in thesemiconductor substrate 1 an n-type semiconductor region 3 as shown inFIG. 9; subsequently, fabricate a p-type well 2 at a shallow portion ofthis n-type semiconductor region 3. The n-type semiconductor region 3 ismanufacturable in a way which follows: The semiconductor substrate 1 isdoped with a chosen impurity, such as phosphorus (P), by ionimplantation techniques at a dose of approximately 1×10¹² atoms persquare centimeter (cm²) with an acceleration energy of 500 to 1,000kilo-electronvolts (KeV); thereafter, the resultant structure is thensubject to thermal processing for activation at a temperature of about1,000° C. The n-type semiconductor region 3 is continuously formed at alevel beneath a plurality of memory cells. In addition, the p-type well2 is fabricated in a way such that a specific impurity—here, boron(B)—is doped by ion implantation techniques into the n-typesemiconductor region 3 at a dose of about 1×10¹³ atoms/cm² with anacceleration energy of 200 to 300 KeV; then, the doped boron (B)impurity is activated through thermal processing at a temperature ofabout 950° C. When this is done, simultaneously perform ion implantationof an impurity (typically, boron fluoride or BF₂) for adjustment of thethreshold voltage of a memory-cell select MISFET Qs at a dose of about2×10¹²/cm² with an acceleration energy of 40 KeV or therearound.

[0094] As shown in FIGS. 10-11, after having removed by wet cleaningtechniques any residual components of the silicon oxide film 30 on thesurface of the active region L, fabricate on the surface of the p-typewell 2 of the active region L a gate oxide film 6 of the memory-cellselect MISFET Qs; then further form thereon a gate electrode 7 (wordline WL). The gate oxide film 6 is formed through wet oxidation of thesurface of the p-type well 2 at a temperature ranging from 800 to 900°C. The gate electrode 7 (word line WL) may be formed by a method thatincludes the steps of depositing by CVD techniques a phosphorus(P)-doped polysilicon film 33 on the semiconductor substrate 1,depositing thereon a TiN film 34 and W film 35 by sputtering techniques,further depositing thereon a silicon nitride film 9 by CVD techniques,and thereafter patterning these films through etching treatment with aphotoresist film used as a mask therefor. As previously stated, the gateelectrode 7 (word line WL) is formed so that it extends like a straightline segment in the Y direction up to the terminate end of a memoryarray while maintaining an identical width (0.24 μm) and equal interval(0.22 μm) along the length thereof.

[0095] Next, as shown in FIG. 12, after completion of fabrication ofn-type semiconductor regions 8 (source, drain) in the p-type well 2 ofthe active region L to thereby form the memory-cell selecting MISFET Qs,use CVD techniques to deposit on this memory-cell select MISFET Qs asilicon nitride film 10 and two silicon oxide films 11, 12. The n-typesemiconductor regions 8 may be formed by a method including the steps ofdoping by ion implantation a phosphorus (P) impurity into the p-typewell at a dose of approximately 1×10¹⁴ atoms/cm² with an accelerationenergy of about 30 KeV, and thereafter applying thermal processingthereto at a temperature of about 900° C. for activation of thephosphorus (P) impurity doped. The overlying silicon oxide film 12 isplanarized to ensure that its surface is virtually identical in heightwith respect to the entire area of the semiconductor substrate 1.

[0096] Next, as shown in FIG. 13, etching is done with a patternedphotoresist film 36 used as a mask to remove selected portions ofsilicon oxide films 12, 11 which overlie the n-type semiconductorregions 8 (source and drain) of each memory-cell select MISFET Qs. Thisetching process is performed under the condition that the etching rateof silicon oxide films 12, 11 with respect to the silicon nitride 10becomes greater while preventing unwanted removal of the silicon nitridefilm 10 overlying the n-type semiconductor regions 8 and elementseparation groove 5.

[0097] Next, as shown in FIGS. 14-15, etching is done with thephotoresist film 36 as a mask to remove away selected portions of thesilicon nitride film 10 and gate oxide film 6 overlying the n-typesemiconductor regions 8 of memory-cell select MISFET Qs to therebyfabricate a contact hole 13 at a location overlying one of the sourceand drain and also a contact hole 14 overlying the other of them. Aspreviously discussed, the contact hole 13 is formed into a pattern ofsubstantially rectangular shape with a diameter in the Y directiongreater than that in the X direction whereas the contact hole 14 isformed to have a pattern with its diameter in the Y direction almostequal to that in the X direction. This etching is done under thecondition that the etching rate of silicon nitride film 10 relative tocertain silicon oxide film (gate oxide film 6 and silicon oxide film 4within the element separation groove 5) becomes greater whileeliminating deep cutaway of the n-type semiconductor regions 8 andelement separation groove 5. This etching is also designed so that thesilicon nitride film 10 is anisotropically etched causing a portion ofsilicon nitride film 10 to reside on the sidewall of a gate electrode 7(word line WL). Through such etching treatment the contact holes 13, 14are formed in self-alignment with the silicon nitride film 10 on thesidewall of gate electrode 7 (word line WL). This formation of suchcontact holes 13, 14 as self-aligned with silicon nitride film 10 mayalternatively be carried out by a method including the steps ofanisotropically etching in advance the silicon nitride film 10 and thenforming a sidewall spacer on the sidewall of gate electrode 7 (word lineWL).

[0098] Next, after having removed the photoresist film 36, form plugs(conductive layers) 15 within the contact holes 13, 14 as shown in FIG.16. These plugs (conductive layers) 15 are manufacturable by depositingon the silicon oxide film 12 a polycrystalline silicon film with ann-type impurity (for example, phosphorus (P)) doped therein by using CVDmethods and thereafter applying chemical-mechanical polishing processingto this polysilicon film thereby letting portions thereof reside insideof the contact holes 13, 14. During later thermal processing at hightemperatures, the n-type impurity doped in the polysilicon filmsconstituting the plugs (conductive layers) 15 behaves to outdiffuse fromthe bottom portions of the contact holes 13, 14 into the n-typesemiconductor regions 8 (source, drain) thereby lowering the electricalresistivity of such n-type semiconductor regions 8.

[0099] Next, as shown in FIGS. 17-18, use CVD methods to deposit on thesilicon oxide film 12 a silicon oxide film 16; thereafter, etch thesilicon oxide film 16 with a patterned photoresist film 37 used as amask to thereby form a through-going hole 17 overlying the contact hole13. As previously stated, the through-hole 17 is formed at a locationthat overlies the element separation groove 5 and is out of the activeregion L. Optionally a plug comprised of a conductive film made of apolysilicon film or W film may be buried in this through-hole 17.

[0100] Next, after having removed the photoresist film 37, fabricateregularly spaced parallel bit lines BL on the silicon oxide film 12 asshown in FIGS. 19-20; then, let each bit line BL be electricallyconnected via the through-hole 17 to the contact hole 13. The bit linesBL are fabricatable by depositing a TiN film and W film by sputteringtechniques on the silicon oxide film 12 and then patterning these filmsthrough etching with a photoresist film used as a mask therefor. Asstated supra, the bit lines BL are so formed as to straightly extendalong the X direction at an equal width (0.14 μm) and an equal interval(0.32 μm).

[0101] Next, as shown in FIG. 21, use CVD techniques to deposit siliconoxide films 18, 19 and silicon nitride film 20 covering the bit linesBL. Apply chemical/mechanical polishing to the silicon oxide film 19 forplanarization so that the resulting surface thereof is keptsubstantially identical in height over the entire area of thesemiconductor substrate 1.

[0102] Next, as shown in FIG. 22, after having deposited on the siliconnitride film 20 a silicon oxide film 38 and a phosphorus (P)impurity-doped polysilicon film 39 by using CVD methods, etching is donewith a photoresist film 40 used as a mask to define openings 25 in thepolysilicon film 39 at specified locations overlying the contact holes14. A respective one of these openings 25 is formed to have a minimalsize as determinable by a limit of resolution in photolithography.

[0103] Next, as shown in FIG. 23, form on the side wall of each opening25 a sidewall spacer 41 made of polysilicon. Formation of the sidewallspacer 41 is aimed at reservation of sufficient opening margins ofthrough-hole 21 as will be formed underlying the opening 25 at a laterprocess step for prevention of unwanted electrical shorting between thebit lines BL and a lower-side electrode 22 within the through-hole 21.The sidewall spacer 41 is formed by depositing on the polysilicon film39 a phosphorus (P)-doped polysilicon film by CVD techniques and thenapply anisotropic etching to this polysilicon film to have a desiredpattern.

[0104] Next, as shown in FIGS. 24-25, use the polysilicon film 39 andsidewall spacers 41 as a mask to sequentially etch selected portions ofthe silicon oxide film 38 and silicon nitride film 20 plus silicon oxidefilms 19, 18, 16 which underlie openings 25 to thereby formthrough-holes 21 each overlying a corresponding contact hole 14. Owingto formation of the sidewall spacers 41 on sidewalls of each opening 25,this through-hole 21 has its diameter that is made finer to the extentthat it is less than the diameter of opening 25—i.e. smaller than theminimal size determinable by the limit of resolution inphotolithography.

[0105] Next, as shown in FIG. 26, after having deposited an n-typeimpurity (e.g. phosphorus (P))-doped polysilicon film 42 by CVD methodto cover the polysilicon film 39 and fill the through-holes 21, depositby CVD methods a silicon oxide film 43 on this polysilicon film 42.

[0106] Next, as shown in FIG. 27, after having removed certain portionsof the silicon oxide film 43 other than those overlying thethrough-holes 21 with a photoresist film used as a mask, deposit by CVDmethods a phosphorus (P)-doped polysilicon film 44 so that it overliesthe polysilicon film 42 including the upper part and sidewalls of thesilicon oxide film 43.

[0107] Next, as shown in FIG. 28, let the polycrystalline silicon films44, 42, 39 be subject to anisotropic etching to allow the polysiliconfilm 44 to reside on sidewall of the silicon oxide film 43 while causingthe polysilicon films 42, 39 to reside at locations underlying thesilicon oxide film 43.

[0108] Next, as shown in FIG. 29, remove by wet etching the siliconoxide film 43 and silicon oxide film 38 to form the lower-side electrode22 of the information accumulation capacitive element C. This etching iscarried out under the condition that the etching rate of the siliconoxide films 43, 38 with respect to the silicon nitride film 20 becomesgreater while at the same time preventing etching of the silicon oxidefilm 19 underlying the silicon nitride film 20.

[0109] Next, as shown in FIG. 30, deposit on the surface of the lowerelectrode 22 a high dielectric film such as tantalum oxide (Ta₂O₅) byCVD methods to thereby fabricate a capacitor insulation film 23 of theinformation accumulation capacitive element C. Thereafter, deposit aphosphorus (P)-doped polysilicon film on the capacitor insulation film23 to form an upper-side electrode 24 of the information accumulationcapacitive element C whereby the DRAM memory cells shown in FIGS. 2-4are thus completed.

[0110] (Embodiment 2 )

[0111] Electrical connection between the n-type semiconductor region 8of a memory-cell selecting MISFET Qs and its associated one of the bitlines BL may alternatively be accomplished in a way as will be describedbelow.

[0112] After having first deposited the silicon nitride film 10 andsilicon oxide films 11, 12 at a level overlying formation of amemory-cell select MISFET Qs in accordance with the procedure at thesteps shown in FIGS. 5 through 12 of the aforesaid Embodiment 1,fabricate through-holes 46 as shown FIGS. 31-32 by etching with aphotoresist film 45 used as a mask, each of which overlies the n-typesemiconductor region 8 (either one of the source and drain) ofmemory-cell select MISFET Qs. While each through-hole 46 is formed tohave a substantially rectangular pattern with its diameter in the Ydirection greater than a diameter in the X direction like the contacthole 13 of the said Embodiment 1, the through-hole is formed shallowerso that its bottom portion is higher in level than gate electrodes 7(word lines WL).

[0113] Next, after having removed the photoresist film 45, as shown inFIGS. 33-34, etching with a second photoresist film 47 used as a mask isdone to form a contact hole 48 overlying either one of the source anddrain of a memory-cell select MISFET Qs and also form a contact hole 49overlying the other of them. These contact holes 48, 49 are each formedto have a pattern that causes a diameter in the Y direction to bevirtually equal to that in the X direction. In addition, the contactholes 48, 49 are formed by two-step etching treatment using the siliconnitride film 10 as an etching stopper in a way similar to that infabrication of the contact holes 13, 14 in said Embodiment 1 to therebypreclude deep cutaway of the n-type semiconductor regions 8 and elementseparation groove 5.

[0114] Next, after removal of the photoresist film 47, make use of thesame methodology as in said Embodiment 1 to form plugs (conductivelayers) 15 within the through-hole 46 and the contact holes 48, 49 asshown in FIG. 35.

[0115] Next, as shown in FIG. 36, use the same method as in saidEmbodiment 1 to form a silicon oxide film 16 on the silicon oxide film12; after fabrication of through-holes 17 by etching of specifiedportions of the silicon oxide film 16 overlying the through-holes 46;form bit lines BL on the silicon oxide film 16. Where appropriate, aplug comprised of a conductive film such as a polysilicon film or w filmmay be buried in each through-hole 17. The following process steps arethe same as those in said Embodiment 1.

[0116] According to the manufacturing method in accordance with theillustrative embodiment, forming on or over the gate electrode 7 (wordline WL) the through-hole 46 having its diameter in the Y directiongreater than the diameter in the X direction while forming beneath thisthrough-hole 46 the contact hole 48 with its diameter in the Y directionalmost identical to the diameter in the X direction permits the area inwhich the plug (conductive layer) 15 buried in the contact hole 48 andthe sidewall of the gate electrode 7 (word line WL) oppose each other tobecomes less than that in said Embodiment 1. This makes it possible toreduce the parasitic capacitance possibly formed between the plug(conductive layer) 15 and gate electrode 7 (word line WL), which in turnenables suppression of word line delay accordingly.

[0117] (Embodiment 3 )

[0118] The through-hole for use in connecting together the through-hole14 as formed overlying the n-type semiconductor region 8 of amemory-cell select MISFET Qs and the lower electrode 22 of aninformation accumulation capacitive element C may alternatively beformed in self-alignment with a corresponding one of the bit lines BL.

[0119] In this case, after having first formed a contact hole 13 ofsubstantially rectangular shape and contact hole 14 of almost squareshape at locations overlying the source and drain of the memory-cellselect MISFET Qs by use of the same method as in said Embodiment 1 asshown in FIG. 37 (a schematical plan view of a semiconductor substratefor indication of part of the memory array thereof) and FIG. 38 (itsleft-side portion is a sectional view along line A-A′ of FIG. 37 whereasthe right side part is a sectional view along line C-C′ of the same) andthen having formed plugs (conductive layers) 15 within them, etch asilicon oxide film 12 deposited on the contact holes 13, 14 to form athrough-hole 17 overlying the element separation groove 5 at a locationout of the active region L.

[0120] Subsequently, form bit lines BL on the silicon oxide film 12;then, make electrical connection between the bit lines BL and the plugs(conductive layers) 15 within the contact holes 13 via respectivethrough-holes 17. The bit lines BL are manufacturable by depositing onthe silicon oxide film 12 a TiN film and W film by sputtering techniquesand then depositing on the W film a silicon nitride film 50 by CVDtechniques and thereafter patterning these films through etching with aphotoresist film used as a mask therefor. The bit lines BL thus formedare such that they straightly extend in the X direction at an equalinterval with an identical width kept along the length thereof.

[0121] The bit lines BL are specifically arranged so that the distanceor interval between adjacent ones thereof is greater than the width ofeach bit line in order to minimize any possible parasitic capacitance asformed between neighboring ones of the bit lines BL for improvement ofinformation read/write rates. For instance, the interval of bit lines BLis set at 0.24 μm. At this time, let the pitch of two neighboring bitlines BL—namely the memory cell size in the Y direction—be set at 0.46μm, which results in the width of a bit line BL being substantiallyequal to 0.22 μm (=0.46−0.24), which may be about the same as theminimum size determinable by a limit of resolution in photolithography.

[0122] Next, as shown in FIG. 39, form on respective side walls of bitlines BL sidewall spacers 51 each made of a silicon nitride film;thereafter, use CVD techniques to sequentially deposit on or over thebit lines BL a silicon oxide film 19 and silicon nitride film 20 plussilicon oxide film 38 in this order. The sidewall spacers 51 may befabricated by anisotropically etching the CVD-deposited silicon nitridefilm overlying the bit lines BL. The silicon oxide film 38 is subjectedto chemical/mechanical polishing processes to ensure that its resultantsurface is kept substantially identical with respect to the entiresurface area of the semiconductor substrate 1.

[0123] Next, as shown in FIG. 40, etch away more than one selectedportion of the silicon oxide film 38 overlying said contact hole 14 witha photoresist film 52 used as a mask. This etching process is done underthe condition that the etching rate of the silicon oxide film 38relative to the silicon nitride film 20 becomes greater while preventingremoval of the silicon nitride film 20.

[0124] Next, as shown in FIG. 41, after having removed the siliconnitride film 20 through etching with the photoresist film 52 used as amask, etch the silicon oxide film 19 and silicon oxide film 16 under thecondition that the etching rate relative to the silicon nitride film 50overlying the bit lines BL and the sidewall spacers 51 comprised ofsilicon nitride film on the sidewalls thereof becomes greater to therebyform through-holes 53 overlying the contact holes 14 in self-alignmentwith the bit lines BL.

[0125] Thereafter, as shown in FIG. 42, fabricate an informationaccumulation capacitive element C with a stacked structure overlying thethrough-hole 53 by the same method as that used in said Embodiment 1,which element consists essentially of a lamination of a lower-sideelectrode (charge accumulation electrode) 22 and capacitor dielectricfilm 23 plus upper-side electrode (plate electrode) 24.

[0126] So far, the present invention made by the inventor(s) has beendescribed in detail based on some illustrative embodiments; however, itshould be noted that the invention should not be limited only to suchembodiments discussed above and may alternatively be modifiable andalterable in a variety of forms without departing from the spirit andscope of the invention.

[0127] Industrial Applicability:

[0128] According to the method for manufacturing a semiconductor of thepresent invention, it becomes possible to retain the requiredsize/dimension accuracy along with resolution margins of photoresistfilms while at the same time enabling successful reduction of any limitsas to on-chip layout of integrated circuit components. This makes itpossible to reduce or “shrink” both the pitch of gate electrodes (wordlines) and the pitch of bit lines thereby enabling miniaturization ofDRAM memory cells, which leads to an ability to accomplish furtherenhanced on-chip integration density. Another advantage of the inventionlies in the capability of reducing the area of a semiconductor chip,which in turn makes it possible to increase production yields of DRAMdevices.

1. A semiconductor integrated circuit device comprising a plurality ofword lines extending in a first direction on a principal surface of asemiconductive substrate, a plurality of bit lines extending in a seconddirection at right angles to the first direction, and an array of memorycells of a DRAM as disposed at cross points of said word lines and saidbit lines, each said memory cell including a serial combination of amemory cell selecting MISFET with a gate electrode as integrally formedwith a corresponding one of said word lines and a capacitive element forinformation accumulation, characterized in that said plurality of wordlines are arranged to linearly extend in the first direction on theprincipal surface of said semiconductive substrate with an identicalwidth, and that a distance between adjacent ones of said word lines isless than said width.
 2. The semiconductor integrated circuit device asrecited in claim 1, characterized in that the distance between theadjacent ones of said gate electrodes is set at a minimal size asdeterminable by a resolution limit of photolithography.
 3. Thesemiconductor integrated circuit device as recited in claim 1,characterized in that said word lines and the gate electrode of saidmemory cell selecting MISFET as integrally formed with a correspondingone of said word lines are comprised of a conductive film at leastpartially including a metallic film therein.
 4. The semiconductorintegrated circuit device as recited in claim 1, characterized in thatsaid semiconductive substrate has an active region with said memory cellselecting MISFET formed therein and being arranged to have anisland-like pattern extending in the second direction on the principalsurface of said semiconductive substrate while having its periphery assurrounded by an element isolation region.
 5. The semiconductorintegrated circuit device as recited in claim 4, characterized in thatthe element isolation region surrounding said active region is formed ofan element separation groove having a dielectric film embedded thereinas defined in the principal surface of said semiconductive substrate. 6.The semiconductor integrated circuit device as recited in claim 1,characterized in that said bit lines are formed overlying said memorycell selecting MISFET with an insulative film laid therebetween, andthat a contact hole for electrical connection between one of a sourceand drain of said memory cell selecting MISFET and a corresponding oneof said bit lines is formed in self-alignment with the gate electrode ofsaid memory cell selecting MISFET.
 7. The semiconductor integratedcircuit device as recited in claim 1, characterized in that saidinformation accumulation capacitive element is formed to overlie saidmemory cell selecting MISFET with an insulative film laid therebetween,and that a contact hole for electrical connection between the other ofthe source and drain of said memory cell selecting MISFET and oneelectrode of said information accumulation capacitive element is formedin self-alignment with the gate electrode of said memory cell selectingMISFET.
 8. A semiconductor integrated circuit device comprising aplurality of word lines extending in a first direction on a principalsurface of a semiconductive substrate, a plurality of bit linesextending in a second direction at right angles to the first direction,and an array of DRAM memory cells as disposed at intersections of saidword lines and said bit lines, each said memory cell including a serialcombination of a memory cell selecting MISFET with a gate electrode asintegrally formed with a corresponding one of said word lines and acapacitive element for information accumulation, characterized in thatsaid bit lines straightly extend in the second direction on theprincipal surface of said semiconductive substrate with an identicalwidth, and that a distance between adjacent ones of said bit lines isgreater than said width.
 9. The semiconductor integrated circuit deviceas recited in claim 8, characterized in that the width of each said bitline is equal to or less than a minimal size determinable by aresolution limit of photolithography.
 10. The semiconductor integratedcircuit device as recited in claim 8, characterized in that said bitlines are comprised of a conductive film at least partially containing ametallic film.
 11. A semiconductor integrated circuit device comprisinga plurality of word lines extending in a first direction on a principalsurface of a semiconductive substrate, a plurality of bit linesextending in a second direction at right angles to the first direction,and an array of DRAM memory cells as disposed at intersections of saidword lines and said bit lines, each said memory cell including a serialcombination of a memory cell selecting MISFET with a gate electrode asintegrally formed with a corresponding one of said word lines and acapacitive element for information accumulation, characterized in thatan active region with said memory cell selecting MISFET formed thereinis arranged to have an island-like pattern extending in the seconddirection on the principal surface of said semiconductive substratewhile having its periphery as surrounded by an element isolation region,that said plurality of word lines extend along the first direction onthe principal surface of said semiconductive substrate with an identicalwidth at an identical distance between adjacent ones thereof, thatcertain one of said bit lines as formed overlying said element isolationregion with a first insulative film laid therebetween extends in thesecond direction on the principal surface of said semiconductivesubstrate with an identical width at a regular distance, and that afirst contact hole for electrical connection between one of a source anddrain of said memory cell selecting MISFET as formed in said activeregion and its associative one of said bit lines as formed overlyingsaid element isolation region has a diameter in the first directiongreater than in the second direction with part thereof arranged toextend to overlie said element isolation region.
 12. The semiconductorintegrated circuit device as recited in claim 11, characterized in thatsaid first contact hole includes a polycrystalline silicon film asformed therein, said polycrystalline silicon film being doped with achosen impurity equal in conductivity type to the source and drain ofsaid memory cell selecting MISFET.
 13. The semiconductor integratedcircuit device as recited in claim 11, characterized in that thecorresponding one of said bit lines and said one of the source and drainof said memory cell selecting MISFET are electrically connected togethervia a first through-hole as formed in a second insulative filmsandwiched between said bit lines and said first insulative film. 14.The semiconductor integrated circuit device as recited in claim 13,characterized in that the width of said bit lines is less than adiameter of said first through-hole.
 15. The semiconductor integratedcircuit device as recited in claim 11, characterized in that said firstcontact hole has a diameter in the first direction greater than in thesecond direction, that part thereof consists essentially of a firstregion extending to overlie said element isolation region and a secondregion as formed beneath said first region to have a diameter in thefirst direction and a diameter in the second direction beingsubstantially equal thereto, and that said first region is formedoverlying said memory cell selecting MISFET.
 16. The semiconductorintegrated circuit device as recited in claim 11, characterized in thatsaid information accumulation capacitive element is formed over said bitlines with a third insulative film laid therebetween and is electricallyconnected to a remaining one of the source and drain of said memory cellselecting MISFET via a second through-hole formed in said thirdinsulative film and a second contact hole as formed in said firstinsulative film at a location underlying said second through-hole. 17.The semiconductor integrated circuit device as recited in claim 16,characterized in that said second contact hole includes apolycrystalline silicon film being embedded therein and doped with animpurity equal in conductivity type to the source and drain of saidmemory cell selecting MISFET.
 18. The semiconductor integrated circuitdevice as recited in claim 16, characterized in that said secondthrough-hole is disposed between neighboring ones of said bit lines andis formed in self-alignment therewith.
 19. A semiconductor integratedcircuit device comprising a semiconductive substrate having a surfaceand an array of memory cells each including a serial combination of asell selecting transistor and a data storage capacitive element withfirst and second electrodes as insulatively laminated over each other,said transistor including a metal insulator semiconductor field effecttransistor (MISFET) having spaced-apart source and drain and aninsulated gate electrode, wherein said device also comprises: word linesinsulatively overlying the surface of said substrate in a firstdirection thereon, said word lines including first, second and thirdword lines each having part making up the gate electrode of the memorycell selecting MISFET; and bit lines insulatively overlying thesubstrate surface in a second direction transverse to the firstdirection, said bit lines including first and second bit lines adjacentto each other, characterized in that the first to third word lines beingsubstantially identical in width and in distance between adjacent onesthereof, said-distance being less than said distance, and said first andsecond bit lines being substantially identical in width and in distancetherebetween, the distance of said first and second bit lines beinggreater than said width thereof.
 20. The semiconductor integratedcircuit device as recited in claim 19, characterized by furthercomprising: a first conductive layer between the first and second wordlines for connecting the first bit line to one of the source and drainof said memory-cell selecting MISFET; a second conductive layer betweenthe second and third word lines for connecting a remaining one of thesource and drain of said memory-cell selecting MISFET to the firstelectrode of said data storage capacitive element; said one of thesource and drain of said memory-cell selecting MISFET and said firstconductive layer being coupled to the first word line and the secondword line in self-alignment therewith; and said remaining one of thesource and drain of said memory-cell selecting MISFET and said secondconductive layer being coupled in self-alignment to the second word lineand the third word line.
 21. A method for manufacturing a semiconductorintegrated circuit device comprising a plurality of word lines extendingin a first direction on a principal surface of a semiconductivesubstrate, a plurality of bit lines extending in a second direction atright angles to the first direction, and an array of DRAM memory cells,as disposed at intersections of said word lines and said bit lines, eachsaid memory cell including a serial combination of a memory cellselecting MISFET with a gate electrode as integrally formed with acorresponding one of said word lines and a capacitive element forinformation accumulation, said method comprising the steps of: (a)forming on the principal surface of said semiconductive substrate of afirst conductivity type an element isolation region and an active regionof island-like pattern having its periphery surrounded by said elementisolation region and extending along the second direction on theprincipal surface of said semiconductive substrate; (b) patterning afirst conductive film formed over the principal surface of saidsemiconductive substrate to form word lines extending in the firstdirection on the principal surface of said semiconductive substrate tohave a distance between adjacent ones thereof being less than a width ofeach said word line; and (c) forming a source and a drain of said memorycell selecting MISFET by introducing an impurity of a secondconductivity type into the principal surface of said semiconductivesubstrate.
 22. The method of forming a semiconductor integrated circuitdevice as recited in claim 21, characterized in that gate electrodes areformed so that a distance between adjacent ones thereof is at a minimalvalue determinable by a limit of resolution in photolithography.
 23. Thesemiconductor integrated circuit device manufacturing method as recitedin claim 21, characterized by including, after said step (c), furtherthe steps of: (d) forming a first insulative film overlying said memorycell selecting MISFET and then forming a second insulative filmoverlying said first insulative film and being different in etching ratefrom said first insulative film; (e) etching those portions of saidsecond insulative film overlying the source and drain of said memorycell selecting MISFET under a condition that the etching rate of saidsecond insulative film with respect to said first insulative filmbecomes greater and then etching said first insulative film overlyingthe source and drain of said memory cell selecting MISFET to therebyform a first contact hole overlying one of said source and drain inself-alignment with said gate electrode to have a diameter in the firstdirection greater than a diameter in the second direction with part ofsaid first contact hole extending toward said element isolation regionwhile forming a second contact hole overlying a remaining one of thesource and drain in self-alignment with said gate electrode and having adiameter in the first direction substantially the same as its diameterin the second direction; (f) after having embedded a conductive film insaid first contact hole and said second contact hole, forming a thirdinsulative film overlying said second insulative film and then forming afirst through-hole in said third insulative film at a portion overlyinga specified region extending to said element isolation region of saidfirst contact hole; and (g) patterning a second conductive film asformed overlying said third insulative film to thereby form bit linesextending along the second direction on the principal surface of saidsemiconductive substrate with an identical width at a distance betweenadjacent ones of said bit lines being greater than said width, and thenelectrically connecting together said first contact hole and acorresponding one of said bit lines via said first through-hole asformed in said third insulative film.
 24. The semiconductor integratedcircuit device manufacturing method as recited in claim 23,characterized in that the width of said bit lines is formed to be equalin dimension to or less than a minimal size determinable by aphotolithography resolution limit while letting the distance betweenadjacent ones of said bit lines be at a minimal size falling within anallowable range of a parasitic capacitance inherently occurredtherebetween.
 25. The semiconductor integrated circuit devicemanufacturing method as recited in claim 23, characterized by including,after said step (g), the steps of: (h) forming a fourth insulative filmoverlying said bit lines and then forming a fifth insulative filmoverlying said fourth insulative film at an etching rate different fromthat of said fourth insulative film; (i) after having etched said fifthinsulative film at a portion overlying said second contact hole under acondition that the etching rate of said fifth insulative film relativeto said fourth insulative film is greater, etching said fourthinsulative film at a portion overlying said second contact hole tothereby form a second through-hole overlying said second contact hole inself-alignment with a corresponding one of said bit lines; and (j)patterning a third conductive film as formed overlying said fifthinsulative film to form a lower-side electrode of an informationaccumulation capacitive element as electrically connected to said secondcontact hole via said second through-hole.